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march 2011 doc id 15389 rev 5 1/52 1 stts2002 2.3 v memory module temperature sensor with a 2 kb spd eeprom features 2.3 v memory module temperature sensor with integrated 2 kb spd eeprom forward compatible with jedec tse 2002a2 and backward compat ible with stts424e02 operating temperature range: ? ?40 c to +125 c single supply voltage: 2.3 v to 3.6 v 2 mm x 3 mm tdfn8, height: 0.80 mm (max) ? jedec mo-229, wced-3 compliant rohs compliant, halogen-free temperature sensor temperature sensor resolution: programmable (9-12 bits) 0.25 c (typ)/lsb - (10-bit) default temperature sensor accuracy (max): ? 1 c from +75 c to +95 c ? 2 c from +40 c to +125 c ? 3 c from ?40 c to +125 c adc conversion time: 125 ms (max) at default resolution (10-bit) typical operating supply current: 160 a (eeprom standby) temperature hysteresis selectable set points from: 0, 1.5, 3, 6.0 c supports smbus timeout 25 ms - 35 ms 2 kb spd eeprom functionality identical to st?s m34e02 spd eeprom permanent and reversible software data protection for the lower 128 bytes byte and page write (up to 16 bytes) self-time write cycle (5 ms, max) automatic address incrementing two-wire bus two-wire smbus/i 2 c - compatible serial interface supports up to 400 khz transfer rate does not initiate clock stretching tdfn8 2 mm x 3 mm (max height 0.80 mm) www.st.com
contents stts2002 2/52 doc id 15389 rev 5 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 serial communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 device type identifier (dti) code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.1 a0, a1, a2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.2 v ss (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.3 sda (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.4 scl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.5 event (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.6 v dd (power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 temperature sensor operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 smbus/i 2 c communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 smbus/i 2 c slave sub-address decoding . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 smbus/i 2 c ac timing consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 temperature sensor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 capability register (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 configuration register (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.1 event thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.2 interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.3 comparator mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.4 shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.5 event output pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.3 temperature register (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3.1 temperature format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.4 temperature trip point registers (read/write) . . . . . . . . . . . . . . . . . . . . . . 25 4.4.1 alarm window trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.4.2 critical trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.5 manufacturer id register (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.6 device id and device revision id register (read-only) . . . . . . . . . . . . . . . 28 4.7 temperature resolution register (read/write) . . . . . . . . . . . . . . . . . . . . . . 29
stts2002 contents doc id 15389 rev 5 3/52 4.8 smbus timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5 spd eeprom operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1 2 kb spd eeprom operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2 internal device reset - spd eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3 memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.4 software write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.4.1 swp and cwp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.4.2 pswp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.5 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.5.1 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.5.2 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.5.3 write cycle polling using ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.6 read operations - spd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.6.1 random address read - spd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.6.2 current address read - spd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.6.3 sequential read - spd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.6.4 acknowledge in read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.7 initial delivery state - spd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6 use in a memory module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.1 programming the spd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.1.1 dimm isolated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.1.2 dimm inserted in the application motherboard . . . . . . . . . . . . . . . . . . . 39 7 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
list of tables stts2002 4/52 doc id 15389 rev 5 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2. ac characteristics of stts2002 for smbus and i 2 c compatibility timings. . . . . . . . . . . . . 15 table 3. temperature sensor registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4. pointer register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5. pointer register select bits (type, width, and default values). . . . . . . . . . . . . . . . . . . . . . . . 17 table 6. capability register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 7. capability register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 8. configuration register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 9. configuration register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 10. hysteresis as applied to temperature movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 11. legend for figure 9: event output boundary timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 12. temperature register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 13. temperature register coding examples (for 10 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 14. temperature register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 15. temperature trip point register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 16. alarm temperature upper boundary register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 17. alarm temperature lower boundary register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 18. critical temperature register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 19. manufacturer id register (read-only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 20. device id and device revision id register (read-only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 21. temperature resolution register (tres) (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 22. tres details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 23. device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 24. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 25. acknowledge when writing data or defini ng the write-protection (instructions with r/w bit = 0)37 table 26. acknowledge when reading the write protection (instructions with r/w bit=1). . . . . . . . . . 38 table 27. dram dimm connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 28. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 29. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 30. dc/ac characteristics - temperature sensor component with eeprom . . . . . . . . . . . . . . 41 table 31. tdfn8 ? 8-lead thin dual flat, no-lead (2 mm x 3 mm) mechanical data (dn) . . . . . . . . . . 44 table 32. parameters for landing pattern - tdfn8 package (dn) . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 33. carrier tape dimensions tdfn8 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 34. reel dimensions for 8 mm carrier tape - tdfn8 package . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 35. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 36. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
stts2002 list of figures doc id 15389 rev 5 5/52 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. tdfn8 connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. smbus/i2c write to pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5. smbus/i 2 c write to pointer register, followed by a read data word. . . . . . . . . . . . . . . . . . . 12 figure 6. smbus/i 2 c write to pointer register, followed by a write data word . . . . . . . . . . . . . . . . . . 13 figure 7. smbus/i 2 c timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8. hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 9. event output boundary timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 10. result of setting the write protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 11. setting the write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 12. write mode sequences in a non write-protected area of spd . . . . . . . . . . . . . . . . . . . . . . 34 figure 13. write cycle polling flowchart using ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 14. read mode sequences - spd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 15. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 16. tdfn8 ? 8-lead thin dual flat, no-lead (2 mm x 3 mm) package outline (dn) . . . . . . . . . . 44 figure 17. dn package topside marking information (tdfn8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 18. landing pattern - tdfn8 package (dn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 19. carrier tape for tdfn8 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 20. reel schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
description stts2002 6/52 doc id 15389 rev 5 1 description the stts2002 is targeted for dimm modules in mobile personal computing platforms (laptops), servers and other industrial applications. the thermal sensor (ts) in the stts2002 is compliant with the jedec specification ts e2002a2, which defines memory module thermal sensors requirements for mobile platforms. the 2 kb serial presence detect (spd) i 2 c-compatible electrically erasable pr ogrammable memory (eeprom) in the stts2002 is organized as 256 x8 bits and is functionally identical to the industry standard m34e02. the ts-spd eeprom combination provides space as well as cost savings for mobile and server platform dual inline memory modules (dimm) manufacturers, as it is packaged in the compact 2 mm x 3 mm 8-lead tdfn package with a thinner maximum height of 0.80 mm. the dn package is compliant to jedec mo-229, variation wced-3. the digital temperature sensor has a progra mmable 9-12 bit analog-to-digital converter (adc) which monitors and digitizes the temperature to a resolution of up to 0.0625 c. the default resolution is 0.25 c/lsb (10-bit). the typical accuracies over these temperature ranges are: 2 c over the full temperature measurement range of ?40 c to 125 c 1 c in the +40 c to +125 c active temperature range, and 0.5 c in the +75 c to +95 c monitor temperature range the temperature sensor in the stts2002 is specified for operating at supply voltages from 2.3 v to 3.6 v. operating at 3.3 v, the typical supply current is 160 a (includes smbus communication current). the on-board sigma delta adc converts the measured temperature to a digital value that is calibrated in c. for fahrenheit applications, a lookup table or conversion routine is required. the stts2002 is factory-calibrated and requires no external components to measure temperature. the digital temperature sensor component has user-programmable registers that provide the capabilities for dimm temperature-sensing applications. the open drain event output pin is active when the monitoring temperature exceeds a programmable limit, or it falls above or below an alarm window. the user has the option to set the event output as a critical temperature output. this pin can be configured to operate in either a comparator mode for thermostat operation or in interrupt mode. the 2 kb serial eeprom memory in the stts2002 has the abilit y to permanently lock the data in its first half (upper) 128 bytes (locations 00h to 7fh). this feature has been designed specifically for use in dram dimms with spd. all of the information concerning the dram module configuration (e.g. access speed, size, and organization) can be kept write protected in the first half of the memory. the second half (lower) 128 bytes of the memory can be write protected using two different software write protection mechanisms. by sending the device a specific sequence, the first 128 bytes of the memory become write protected: permanently or resettable. in the stts2002 the write protection of the memory array is dependent on whether the software protection has been set.
stts2002 serial communications doc id 15389 rev 5 7/52 2 serial communications the stts2002 has a simple 2-wire smbus/i 2 c-compatible digital se rial interface which allows the user to access both the 2 kb seri al eeprom and the data in the temperature register at any time. it communicates via the serial interface with a master controller which operates at speeds of up to 400 khz. it also gives the user easy access to all of the stts2002 registers in order to customize device operation. 2.1 device type identifier (dti) code the jedec temperature s ensor and eeprom each have their own unique i 2 c address, which ensures that there are no compatibility or data tran slation issues. this is due to the fact that each of the devices have their own 4-bit dti code, while the remaining three bits are configurable. this enables the eeprom and thermal sensors to provide their own individual data via their unique addresses and still not interfere with ea ch other?s operation in any way. the dti codes are: '0011' for the ts, and '1010' for addressing the eeprom memory array, and ?0110? to access the so ftware write protection settings of the eeprom.
serial communications stts2002 8/52 doc id 15389 rev 5 figure 1. logic diagram 1. sda and event are open drain. note: see section 2.2: pin descriptions on page 10 for details. figure 2. tdfn8 connections (top view) 1. sda and event are open drain. table 1. signal names pin symbol description direction 1 a0 serial bus address selection pin. can be tied to v ss or v dd . input 2 a1 serial bus address selection pin. can be tied to v ss or v dd . input 3 a2 serial bus address selection pin. can be tied to v ss or v dd . input 4v ss supply ground 5sda (1) 1. sda and event are open drain. serial data input/output 6 scl serial clock input 7 event (1) event output pin. open drain and active-low. output 8v dd supply power (2.3 v to 3.6 v) ai12261 sda (1) v dd stts2002 v ss scl event (1) a 2 a 1 a 0 1 sda (1) gnd scl event (1) a1 a0 v dd a2 ai12262 2 3 4 8 7 6 5
stts2002 serial communications doc id 15389 rev 5 9/52 figure 3. block diagram temperature sensor adc address pointer register 1 2 3 4 5 6 capability register configuration register temperature register upper register lower register critical register manufacturer id device id/ revision logic control comparator timing smbus/i 2 c interface software write-protected array (00h - 7fh) 7 8 v dd scl sda a0 a1 a2 v ss event ai12278a standard array (80h - ffh) 2 kb spd eeprom
serial communications stts2002 10/52 doc id 15389 rev 5 2.2 pin descriptions 2.2.1 a0, a1, a2 a2, a1, and a0 are selectable address pins for the 3 lsbs of the i 2 c interface address. they can be set to v dd or gnd to provide 8 unique address selections. these pins are internally connected to the e2, e1, e0 (chip selects) of eeprom. 2.2.2 v ss (ground) this is the reference for the power supply. it must be connected to system ground. 2.2.3 sda (open drain) this is the serial data input/output pin. 2.2.4 scl this is the serial clock input pin. 2.2.5 event (open drain) this output pin is open drain and active-low. 2.2.6 v dd (power) this is the supply voltage pin, and ranges from 2.3 v to 3.6 v.
stts2002 temperature sensor operation doc id 15389 rev 5 11/52 3 temperature sensor operation the temperature sensor continuously monitors the ambient temperature and updates the temperature data register. temperature data is latched internally by the device and may be read by software from the bus host at any time. the smbus/i 2 c slave address selection pins allow up to 8 such devices to co-exist on the same bus. this means that up to 8 memory modules can be supported, given that each module has one such slave device address slot. after initial power-on, the configuration registers are set to the default values. the software can write to the configuration register to set bits per the bit definitions in section 3.1: smbus/i 2 c communications . for details of operation and usage of 2 kb spd eeprom, refer to section 5: spd eeprom operation . 3.1 smbus/i 2 c communications the registers in this device are selected by the pointer register. at power-up, the pointer register is set to ?00?, which is the capability register location. the poi nter register latches the last location it was set to. each data register falls into one of three types of user accessibility: 1. read-only 2. write-only, and 3. write/read same address a write to this device will always include t he address byte and the pointer byte. a write to any register other than the pointer register, requires two data bytes. reading this device is achieved in one of two ways: if the location latched in the pointer register is correct (most of the time it is expected that the pointer register will po int to one of the read temperature regi sters because that will be the data most freq uently read), then th e read can simply c onsist of an address byte, followed by retrieval of the two data bytes. if the pointer register needs to be set, then an address byte, pointer byte, repeat start, and another address byte will accomplish a read. the data byte transfers the msb first. at the end of a read, this device can accept either an acknowledge (ack) or no acknowledge (no ack) status from the master. the no ack status is typically used as a signal for the slave that the master has read its last byte. this device subsequently takes up to 125 ms to measure the temperature for the default temperature resolution. note: stts2002 does not initiate clock stretching which is an optional i 2 c bus feature.
temperature sensor operation stts2002 12/52 doc id 15389 rev 5 figure 4. smbus/i 2 c write to pointer register figure 5. smbus/i 2 c write to pointer register, followed by a read data word ai12264 11 99 0 start by master address byte pointer byte ack by stts2002 ack by stts2002 0 1 1 a2 a1 a0 r/w 0 0 0 0 0 d2 d1 d0 scl sda ai12265 1919 ack by master no ack by master stop cond. by master d7 d6 d5 d4 d3 d2 d1 d0 msb data byte lsb data byte 11 99 0 start by master address byte pointer byte ack by stts2002 ack by stts2002 0 1 1 a2 a1 a0 r/w 0 0 0 0 0 d2 d1 d0 scl sda d9 d10 d11 d12 d13 d14 d15 d8 19 repeat start by master ack by stts2002 0 0 1 1 a2 a1 a0 r/w address byte scl (continued) sda (continued)
stts2002 temperature sensor operation doc id 15389 rev 5 13/52 figure 6. smbus/i 2 c write to pointer register, followed by a write data word 3.2 smbus/i 2 c slave sub-address decoding the physical address for the ts is different than th at used by the eeprom. the ts physical address is binary 0011a2a1a0rw, where a2, a1, and a0 are the three slave sub- address pins, and the lsb ?rw? is the read/write flag. the eeprom physical address is binary 1 010a2a1a0rw for the memory array and is 0110a2a1a0rw for permanently set write protection mode. ai14012 1919 ack by stts2002 no ack by stts2002 stop cond. by master d7 d6 d5 d4 d3 d2 d1 d0 msb data byte lsb data byte 11 99 0 start by master address byte pointer byte ack by stts2002 ack by stts2002 0 1 1 a2 a1 a0 r/w 0 0 0 0 0 d2 d1 d0 scl scl (continued) sda d8 d9 d10 d11 d12 d13 d14 d15 sda (continued)
temperature sensor operation stts2002 14/52 doc id 15389 rev 5 3.3 smbus/i 2 c ac timing consideration in order for this device to be both smbus- and i 2 c-compatible, it comp lies to a subset of each specification. th e requirements which enable this device to co-exist with devices on either an smbus or an i 2 c bus include: the smbus minimum clock frequency is required. the smbus timeout is maximum 35 ms (temperature sensor only). figure 7. smbus/i 2 c timing diagram v ih v ih v ih v ih v il v il v il v il s cl s cl s da s da note: p s t a nd s for s top a nd s s t a nd s for s ta rt s top condition write cycle s ta rt condition t s u: s ta t s u: s to t w t buf t low t hd: s ta t hd:di t r t f t s u:dat t high t s u: s ta t hd:dat t s u: s to p s p s a i12266 a
stts2002 temperature sensor operation doc id 15389 rev 5 15/52 table 2. ac characteristics of stts2002 for smbus and i 2 c compatibility timings symbol parameter min max units f scl smbus/i 2 c clock frequency 10 400 khz t high clock high period 600 ? ns t low (1) 1. stts2002 will not initiate clock stretching which is an i 2 c bus optional feature. clock low period 1300 ? ns t r (2) 2. guaranteed by design and characte rization, not necessarily tested. clock/data rise time ? 300 ns t f (2) clock/data fall time 20 300 ns t su:dat data in setup time 100 ? ns t hd:di data in hold time 0 ? ns t hd:dat data out hold time 200 900 ns t su:sta (3) 3. for a restart condition, or following a write cycle. repeated start condition setup time 600 ? ns t hd:sta hold time after (repeated) start condition. after this period, the first clock cycle is generated. 600 ? ns t su:sto stop condition setup time 600 ? ns t buf bus free time between stop (p) and start (s) conditions 1300 ? ns t w (4) 4. this parameter reflects maximum write time for eeprom. write time for eeprom ? 10 ms t timeout (5) 5. bus timeout value supported depends on setting of tmout bit 6 in capability register. bus timeout (temperature sensor only) 25 35 ms
temperature sensor registers stts2002 16/52 doc id 15389 rev 5 4 temperature sensor registers the temperature sensor component is comprised of various user-programmable registers. these registers are required to write their corresponding addresses to the pointer register. they can be accessed by writing to their respective addresses (see ta bl e 3 ). pointer register bits 7 - 4 must always be written to '0' (see ta b l e 4 ). this must be maintained, as not setting these bits to '0' may keep the device from performing to specifications. the main registers include: capability register (read-only) configuration register (read/write) temperature register (read-only) temperature trip point registers (read/write) , including ? alarm temperature upper boundary, ? alarm temperature lower boundary, and ? critical temperature. manufacturer id register (read-only) device id and device revision id register (read-only) temperature resolution register (tres) (read/write) see table 5 on page 17 for pointer register selection bit details. note: registers beyond the specified (00-08) are reserved for stmicroelectronics internal use only, for device test modes in product manufacturing. the registers must not be accessed by the user (customer) in the system applicati on or the device may not perform according to specifications. table 3. temperature sensor registers summary address (hex) register name power-on default not applicable address pointer undefined 00 capability b-grade 0x006f 01 configuration 0x0000 02 alarm temperature upper boundary trip 0x0000 03 alarm temperature lower boundary trip 0x0000 04 critical temperature trip 0x0000 05 temperature undefined 06 manufacturer?s id 0x104a 07 device id/revision 0x0300 08 temperature resolution register 0x0001
stts2002 temperature sensor registers doc id 15389 rev 5 17/52 4.1 capability register (read-only) this 16-bit register is read-only, and provides the ts capabilities which comply with the minimum jedec tse2002a2 specifications (see ta bl e 6 and table 7 on page 18 ). the stts2002 resolution is programmable via writing to pointer 08 register. the power-on default value is 0.25 c/lsb (10-bit). table 4. pointer register format msb lsb bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0 0 0 0 p3p2p1p0 pointer/register select bits table 5. pointer register select bits (type, width, and default values) p3 p2 p1 p0 name register description width (bits) type (r/w ) default state (por) 0000capa thermal sensor capabilities b-grade only 16 r 00 6f 0001conf configuration 16 r/w 00 00 0010upper alarm temperature u pper boundary 16 r/w 00 00 0011lower alarm temperature lower boundary 16 r/w 00 00 0100criticalcritical temperature 16 r/w 00 00 0101temp temperature 16 r 00 00 0110manu manufacturer id 16 r 10 4a 0111id device id/revision 16 r 03 00 1000tres temperature resolution register 8 r/w 01 table 6. capability register format bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 rfu rfu rfu rfu rfu rfu rfu rfu bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 evsd tmout v hv tres1 tres0 wider range higher precision alarm and critical trips
temperature sensor registers stts2002 18/52 doc id 15389 rev 5 table 7. capability register bit definitions bit definition 0 basic capability ? 0 = alarm and critical trips turned off. ? 1 = alarm and criti cal trips turned on. 1 accuracy ? 0 = accuracy 2 c over the active range and 3 c over the monitoring range (c-grade). ? 1 = high accuracy 1 c o ver the active range and 2 c over the monitoring range (b-grade) (default) . 2 range width ? 0 = values lower than 0 c will be clamped and represented as binary value '0'. ? 1 = temperatures below 0 c can be read and the sign bit will be set accordingly. 4:3 temperature resolution ? 00 = 9 bit, 0.5 c/lsb ? 01 = 10 bit, 0.25 c/lsb - default resolution ? 10 = 11 bit, 0.125 c/lsb ? 11 = 12 bit, 0.0625 c/lsb 5 (v hv ) high voltage support for a0 (pin 1) ?1 = stts2002 supports a voltage up to 10 vo lts on the a0 pin - (default) 6 tmout - bus timeout support (for temperature sensor only) ?0 = t timeout is supported in the range of 10 to 60 ms ?1 = default for stts2002-smbus compatible 25 ms - 35 ms note: timeout is not required for eeprom component 7 evsd - event behavior upon shutdown ? 0 = default for stts2002. the event output freezes in it s current state when entering shutdown. upon entering shutdown, the event output remains in the previous state until the next thermal data conversion or possibly sooner if event is programmed for comparator mode. ? 1 = event output is deasserted (not driven) when entering shutdown and remains deasserted upon exit from shutdown until the next thermal sample is taken or possibly sooner if event is programmed for comparator mode. 15:8 reserved these values must be set to '0'.
stts2002 temperature sensor registers doc id 15389 rev 5 19/52 4.2 configuration register (read/write) the 16-bit configuration register stores various configuration modes that are used to set up the sensor registers and configure according to application and jedec requirements (see table 8 on page 19 and table 9 on page 20 ). 4.2.1 event thresholds all event thresholds use hysteresis as programm ed in register address 0x01 (bits 10 through 9) to be set when they de-assert. 4.2.2 interrupt mode the interrupt mode allows an event to occur where software may write a '1' to the clear event bit (bit 5) to de-assert the event interrupt output until the next trigger condition occurs. 4.2.3 comparator mode comparator mode enables the device to be used as a thermostat. reads and writes on the device registers will not affect the event ou tput in comparator m ode. the event signal will remain asserted until temperature drops outside the range or is re-programmed to make the current temperature ?out of range?. 4.2.4 shutdown mode the stts2002 features a shutdown mode which disables all power-consuming activities (e.g. temperature sampling operations), and leaves the serial interface active. this is selected by setting shutdown bit (bit 8) to '1'. in this mode, the devices consume the minimum current (i shdn ), as shown in table 30 on page 41 . note: bit 8 cannot be set to '1' while bits 6 and 7 (the lock bits) are set to '1'. the device may be enabled for continuous operation by clearing bit 8 to '0'. in shutdown mode, all registers may be read or written to. power recyclin g will also clear this bit and return the device to continuous mode as well. table 8. configuration register format bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 rfu rfu rfu rfu rfu hysteresis hysteresis shutdown mode bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 critical lock bit alarm lock bit clear event event output status event output control critical event only event polarity event mode
temperature sensor registers stts2002 20/52 doc id 15389 rev 5 table 9. configuration re gister bit definitions bit definition 0 event mode ? 0 = comparator output mo de (this is the default). ? 1 = interrupt mode; when either of t he lock bits (bit6 or bit7) is set, th is bit cannot be altered until it is unlocked. 1 event polarity (1) the event polarity bit controls the active state of the event pin. the event pin is driv en to this state when it is asserted. ? 0 = active-low (this is the default). requires a pull -up resistor to set the in active state of the open- drain output. the power to the pull-up resistor should not be greater than v dd + 0.2 v. active state is logical ?0?. ? 1 = active-high. the active state of the pin is then logical ?1?. 2 critical event only ? 0 = event output on alarm or critical temperature event (th is is the default). ? 1 = event only if the temperature is above t he value in the critical temperature register (t a > t crit ); when the alarm window lock bit (bit6) is set, this bit cannot be altered until it is unlocked. 3 event output control ? 0 = event output disabl ed (this is the default). ? 1 = event output enabled; when either of the lock bits (bit 6 or bit7) is set, this bit cannot be altered until it is unlocked. 4 event status (read-only) (2) ? 0 = event output condition is not being asserted by this device. ? 1 = event output condition is being asserted by this device via the alarm window or critical trip event. 5 clear event (write-only) (3) ? 0 = no effect. ? 1 = clears the active event in interrupt mode. the pin is released and will not assert until a new interrupt condition occurs. 6 alarm window lock bit ? 0 = alarm trips are not locked and can be altered (this is the default). ? 1 = alarm trip register settings cannot be altered. this bit is initially cleared. when set, this bit returns a logic '1' and remains locked until cleared by an internal power-on reset. these bits can be written to with a single write, and do not require double writes. 7 critical trip lock bit ? 0 = critical trip is not locked an d can be altered (th is is the default). ? 1 = critical trip register settings cannot be altered. th is bit is initially cleared. when set, this bit returns a logic '1' and remains locked until cleared by an internal power-on reset. these bits can be written to with a single write, and do not require double writes. 8 shutdown mode ? 0 = ts is enabled, continuous conversion (this is the default). ? 1 = shutdown ts when the shutdown, device, and a/d converter are disabled in order to save power. no event conditions will be asserted; when either of the lock bits (bit6 or bit7) is set, then this bit cannot be altered until it is unlocked. it can be cleared at any time.
stts2002 temperature sensor registers doc id 15389 rev 5 21/52 figure 8. hysteresis 1. t h = value stored in the alarm te mperature upper boundary trip register 2. t l = value stored in the alarm temperature lower boundary trip register 3. hys = absolute value of selected hysteresis 10:9 hysteresis enable (see figure 8 and ta bl e 1 0 ) ? 00 = hysteresis is disabled (default) ? 01 = hysteresis is enabled at 1.5 c ? 10 = hysteresis is enabled at 3 c ? 11 = hysteresis is enabled at 6 c hysteresis applies to all limits when the temperatur e is dropping below the threshold so that once the temperature is above a given threshold, it must drop below the threshold minus the hysteresis in order to be flagged as an interrupt event . note that hysteresis is also applied to the event pin functionality. when either of the lock bits is se t, these bits cannot be altered. 15:11 reserved for future use. these bits will always read ?0? and writing to them will have no effect. for future compatibility, all rfu bits must be programmed as ?0?. 1. as this device is used in dimm (memory modules) applications, it is strongly recommended that only the active-low polarity (default) is used. this will provide fu ll compatibility with the stts424e02. th is is the recommended configuration for the stts2002. 2. the actual incident causing the event can be determined fr om the read temperature register. interrupt events can be cleared by writing to the clear event bi t (writing to this bit will have no effect on overall device functioning). 3. writing to this register has no effect on overall device functioning in comparat or mode. when read, this bit will always return a logic '0' result. table 9. configuration register bit definitions (continued) bit definition below window bit above window bit t h - hys t l - hys t h t l ai12270 table 10. hysteresis as applied to temperature movement below alarm window bit above alarm window bit temperature slope temperature threshold temperature slope temperature threshold sets falling t l - hys rising t h clears rising t l falling t h - hys
temperature sensor registers stts2002 22/52 doc id 15389 rev 5 4.2.5 event outpu t pin functionality the stts2002 event pin is an open drain output that requires a pull-up to v dd on the system motherboard or in tegrated into the ma ster controller. event has three operating modes, depending on configuration settings and any current out-of-limit conditions. these modes are interrupt, comparator or critical. in interrupt mode the event pin will remain asserted until it is released by writing a ?1? to the ?clear event? bit in the status register. the value to write is independent of the event polarity bit. in comparator mode the event pin will clear itself when the er ror condition that caused the pin to be asserted is removed. in the critical mode the event pin will only be asserted if the measured temperature exceeds the critical limit. once the pin has bee n asserted, it will remain asserted until the temperature drops below the critical limit minus hysteresis. figure 9 on page 23 illustrates the operation of the different modes over time and temperature. when the hysteresis bits (bits 10 and 9) are enabled, hysteresis may be used to sense temperature movement around trigger points. for example, when using the ?above alarm window? bit (temperature register bit 14, see table 12 on page 24 ) and hysteresis is set to 3 c, as the temperature rises, bit 14 is set (bit 14 = 1). the temperature is above the alarm window and the temperature register contains a value that is greater than the value set in the alarm temperature upper boundary register (see table 16 on page 26 ). if the temperature decreases, bi t 14 will remain set until the m easured temperat ure is less than or equal to the value in the alarm temperature upper boundary register minus 3 c (see figure 8 on page 21 and table 10 on page 21 for details. similarly, when using the ?below alarm window? bit (temperature register bit 13, see table 12 on page 24 ) will be set to '0'. the tem perature is equal to or great er than the value set in the alarm temperature lower boundary register (see table 17 on page 26 ). as the temperature decreases, bit 13 will be set to '1 ' when the value in the temperat ure register is less than the value in the alarm temperature lower boundary register minus 3 c (see figure 8 on page 21 and table 10 on page 21 for details. the device will retain the previo us state when entering the sh utdown mode. if the device enters the shutdown mode while the event pin is low, the shutdo wn current will increase due to the additional event output pull-down current.
stts2002 temperature sensor registers doc id 15389 rev 5 23/52 figure 9. event output boundary timings systems that use the active high mode for event output must be wired point-to-point between the stts2002 and the sensing controller. wire-or configurations should not be used with active high event output since an y device pulling the event output signal low will mask the other devices on the bus. also note that the normal state of event output in active high mode is a ?0? which will constantly dr aw power through th e pull-up resistor. table 11. legend for figure 9: event output boundary timings note event output boundary conditions event output t a bits comparator interrupt critical 15 14 13 1t a t lower h l h 000 2t a < t lower - t hys l l h 001 3t a > t upper l l h 010 4t a t upper - t hys h l h 000 5t a t crit l l l 100 6t a < t crit - t hys l h h 010 7 when t a t crit and t a < t crit - t hys , the event output is in comparator mode and bit 0 of the configuration register (i nterrupt mode) is ignored. comparator t crit t upper t lower t a t lower - t hys interrupt s/w int. clear critical event output (active low) t upper - t hys t crit - t hys t upper - t hys t lower - t hys 1213357 4642 ai12271 note:
temperature sensor registers stts2002 24/52 doc id 15389 rev 5 4.3 temperature register (read-only) this 16-bit, read-only register stores the temperature measured by the internal band gap ts as shown in ta bl e 1 2 . when reading this register, the msbs (bit 15 to bit 8) are read first, and then the lsbs (bit 7 to bit 0) are read. the result is the current-sensed temperature. the data format is 2s complement with one lsb = 0.25 c for the default resolution. the msb has a 128 c resolution. the trip status bits represent the internal temperature trip detection, and are not affected by the status of the event or configuration bits (e.g. event output control or clear event). if neither of the above or below values are set (i.e. both are 0), then the temperature is exactly within the user-defined alarm window boundaries. 4.3.1 temperature format the 16-bit value used in the trip point set and temperature read-back registers is 2s complement, with the lsb equal to 0.0625 c (see ta bl e 1 2 ). for example: 1. a value of 019c h represents 25.75 c, 2. a value of 07c0 h represents 124 c, and 3. a value of 1e74 h represents ?24.75 c all unused resolution bits are set to zero . the msb will have a resolution of 128 c. the stts2002 supports programmable resolutions (9-12 bits) which is 0.5 to 0.0625 c/lsb. the default is 0.25 c/lsb (10 bits) programmable. the upper 3 bits indicate trip status based on the current temperature, and are not affected by the event output status. table 12. temperature register format sign msb lsb (1) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 (2) bit 0 (3) flag bit flag bit flag bit sign 128 64 32 16 8 4 2 1 0.5 0.25 0.125 0.0625 c/lsb above critical input (4) above alarm window (4) below alarm window (4) temperature (default - 10 bit) 0 0 flag bits example hex value of 07c0 corresponds to 124 c (10-bit) 0 0 0 0 0 11111000 0 0 0 07c0 h flag bits example hex value of 1d80 corresponds to ?40 c (10-bit) 0 0 0 1 1 10110000 0 0 0 1d80 h 1. bit 2 is lsb for default 10-bit mode. 2. depending on status of the resolution register, bit 1 may display 0.125 c value. 3. depending on status of the resolution register, bit 0 may display 0.0625 c value. 4. see table 14 for explanation.
stts2002 temperature sensor registers doc id 15389 rev 5 25/52 a 0.25 c minimum granularity is supported in all registers. examples of valid settings and interpretation of temperature register bits for 10-bit (0.25 c) default resolution are provided in ta b l e 1 3 . 4.4 temperature trip point registers (read/write) the stts2002 alarm mode registers provide for 11-bit data in 2s compliment format. the data provides for one lsb = 0.25 c. all unused bits in these registers are read as '0'. the stts2002 has three temperature trip point registers (see ta b l e 1 5 ): alarm temperature upper boundary threshold ( ta bl e 1 6 ), alarm temperature lower boundary threshold ( ta b l e 1 7 ), and critical temperature trip point value ( ta b l e 1 8 ). note: if the upper or lower boundar y threshold values are being al tered in-system, all interrupts should be turned off until a known state can be obtained to avoid superfluous interrupt activity. table 13. temperature register coding examples (for 10 bits) b15:b0 (binary) value units xxx0 0000 0010 11xx +2.75 c xxx0 0000 0001 00xx +1.00 c xxx0 0000 0000 01xx +0.25 c xxx0 0000 0000 00xx 0 c xxx1 1111 1111 11xx ?0.25 c xxx1 1111 1110 00xx ?1.00 c xxx1 1111 1101 11xx ?2.25 c table 14. temperature register bit definitions bit definition with hysteresis = 0 13 below (temperature) alarm window ? 0 = temperature is equal to or above the alarm window lower boundary temperature. ? 1 = temperature is below the alarm window. 14 above (temperature) alarm window. ? 0 = temperature is equal to or below the alarm window upper boundary temperature. ? 1 = temperature is above the alarm window. 15 above critical trip ? 0 = temperature is below the critical temperature setting. ? 1 = temperature is equal to or above the critical temperature setting.
temperature sensor registers stts2002 26/52 doc id 15389 rev 5 4.4.1 alarm window trip the device provides a comparison window with an upper temperature trip point in the alarm upper boundary register, and a lower trip point in the alarm lower boundary register. when enabled, the event output will be triggered whenever entering or exiting (crossing above or below) the alarm window. 4.4.2 critical trip the device can be programmed in such a way that the event output is only triggered when the temperature exceeds the critical trip point. the critical temperature setting is programmed in the critical temperature register. when the temperature sensor reaches the critical temperature value in this register, the device is automatically placed in comparator mode, which means that the critical event output cannot be cleared by using software to set the clear event bit. table 15. temperature trip point register format p3 p2 p1 p0 name register description width (bits) type (r/w ) default state (por) 0 0 1 0 upper alarm temperature upper boundary 16 r/w 00 00 0 0 1 1 lower alarm temperature lower boundary 16 r/w 00 00 0 1 0 0 critical critical temperature 16 r/w 00 00 table 16. alarm temperature upper boundary register format sign msb lsb (1) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit (2) 1 bit (3) 0 000 alarm window upper boundary temperature 00 1. bit 2 is lsb for default 10-bit mode. 2. depending on status of the resolution register, bit 1 may display 0.125 c value. 3. depending on status of the resolution register, bit 0 may display 0.0625 c value. table 17. alarm temperature lower boundary register format sign msb lsb (1) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit (2) 1 bit (3) 0 000 alarm window lower boundary temperature 00 1. bit 2 is lsb for default 10-bit mode. 2. depending on status of the resolution register, bit 1 may display 0.125 c value. 3. depending on status of the resolution register, bit 0 may display 0.0625 c value.
stts2002 temperature sensor registers doc id 15389 rev 5 27/52 note: in all temperature register formats bits 0 and bits 1 are used when the resolution is more than 10 bits. these registers show temperature data for the default 10 bits. table 18. critical temperature register format sign msb lsb (1) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit (2) 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit (3) 1 bit (4) 0 000 critical temperature trip point 00 1. bit 2 is lsb for default 10-bit mode. 2. if critical trip lockout bit (bit 7 of configurat ion register in table 9 ) is set, then this regi ster becomes read-only. 3. depending on status of the resolution register, bit 1 may display 0.125 c value. 4. depending on status of the resolution register, bit 0 may display 0.0625 c value.
temperature sensor registers stts2002 28/52 doc id 15389 rev 5 4.5 manufacturer id register (read-only) the manufacturer?s id (programmed value 104ah) in this register is the stmicroelectronics identification provided by the peripheral component interconnect special interest group (pcisig). 4.6 device id and device revision id register (read-only) the device ids and device revision ids are maintained in this register. the register format is shown in ta b l e 2 0 . the device ids and device revision ids are currently '0' and will be incremented whenever an update of the device is made. the current device id and revision id value is 0300 h. table 19. manufacturer id register (read-only) bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 00010000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01001010 table 20. device id and device revision id register (read-only) bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 00000011 device id bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000000 device revision id
stts2002 temperature sensor registers doc id 15389 rev 5 29/52 4.7 temperature resolution register (read/write) with this register a user can program the temperature sensor resolution from 9-12 bits as shown below. the power-on default is always 10 bit (0.25 c/lsb). the selected resolution is also reflected in bits (4:3) (tr es1:tres0) of the capability register. the default value is 01 for tres register. 4.8 smbus timeout the stts2002 supports the smbus timeout feature which is turned on by default. if the host holds scl low for more than t timeout (max), the stts2002 resets itself and releases the bus. this feature is supported even when the device is in shutdown mode and when the device is driving sda low. table 21. temperature resolution register (tres) (read/write) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000001 resolution section register resolution bits table 22. tres details resolution re gister bits bit1 bit0 c/lsb bits conversion time (max) 0 0 0.5 9 65 ms 0 1 0.25 10 125 ms (default) 1 0 0.125 11 250 ms 1 1 0.0625 12 500 ms
spd eeprom operation stts2002 30/52 doc id 15389 rev 5 5 spd eeprom operation 5.1 2 kb spd eeprom operation the 2 kb serial eeprom is able to lock perman ently the data in its first half (from location 00h to 7fh). this feature has been designed s pecifically for use in dram dimms (dual in line memory modules) with serial presence detect. all the information concerning the dram module configuration (such as its access speed, its size, its organization) can be kept write protected in the first half of the memory. the first half of the memory area can be write-protected using two different software write protection mechanisms. by sending the device a specific sequence, the first 128 bytes of the memory become write protected: permanently or resetable. these i 2 c-compatible electrically erasable pr ogrammable memory (eeprom) devices are organized as 256x8 bits. i 2 c uses a two wire serial interface, comprising a bidirectional data line and a clock line. the device carries a built-in 4-bit device type identifier code (1010) in accordance with the i 2 c bus definition to access the memory area and a second device type identifier code (0110) to define the protection. these codes are used together with the voltage level applied on the three chip enable inputs (a2, a1, a0). these input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code. in the end application, a0, a1 and a2 must be directly (not through a pull-up or pull-down resistor) connected to v dd or v ss to establish the device select code. when these inputs are not connected, an internal pull-down circuitry makes (a0, a1, a2) = (0,0,0). the a0 input is used to detect the v hv voltage, when decoding an swp or cwp instruction (refer to table 23: device select code ). the device behaves as a slave device in the i 2 c protocol, with all memory operations synchronized by the serial clock. read and write operations are initiated by a start condition, generated by the bus master. the st art condition is followed by a device select code and rw bit (as described in table 23: device select code ), terminated by an acknowledge bit. when writing data to the memory, the memory inserts an acknowledge bit during the 9 th bit time, following the bus master?s 8-bit transmission. when data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. data transfers are terminated by a stop condition after an ack for write, and after a noack for read. 5.2 internal device reset - spd eeprom in order to prevent inadvertent write operations during power-up, a power on reset (por) circuit is included. at power-up (phase during which v dd is lower than v dd min but increases continuously), the device will not respond to any instruction until v dd has reached the power on reset threshold voltage (this threshold is lower than the minimum v dd operating voltage defined in table 2: ac characteristics of stts2002 for smbus and i 2 c compatibility timings ). once v dd has passed the por threshol d, the device is reset.
stts2002 spd eeprom operation doc id 15389 rev 5 31/52 prior to selecting the memory and issu ing instructions, a valid and stable v dd voltage must be applied. this voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (t w ). at power-down (phase during which v dd decreases continuously), as soon as v dd drops from the normal operating voltage below the power on reset threshold voltage, the device stops responding to any instruction sent to it. 5.3 memory addressing to start communication between the bus master and the slave device, the bus master must initiate a start condition. follo wing this, the bus master sends the device select code, shown in table 23: device select code (on serial data (sda), most significant bit first). the device select code consists of a 4-bit device type identifier, and a 3-bit chip enable ?address? (a2, a1, a0). to address the memory array, the 4-bit device type identifier is 1010b; to access the write-protection settings, it is 0110b. up to eight memory devices can be connected on a single i 2 c bus. each one is given a unique 3-bit code on the chip enable (a0, a1, a2) inputs. when the device select code is received, the device only responds if the chip enable address is the same as the value on the chip enable (a0, a1, a2) inputs. the 8 th bit is the read/write bit (rw ). this bit is set to 1 for read and 0 for write operations. if a match occurs on the device select code, the corresponding device gives an acknowledgment on serial data (sda) during the 9 th bit time. if the device does not match the device select code, it deselects itself from the bus, and goes into standby mode. the operating modes are detailed in ta bl e 2 4 . table 23. device select code chip enable signals device type identifier chip enable bits rw b7 (1) 1. the most significant bit, b7, is sent first. b6 b5 b4 b3 b2 b1 b0 memory area select code (two arrays) (2) 2. a0, a1 and a2 are compared against the respec tive external pins on the memory device. a2a1a01010a2a1a0rw set write protection (swp) v ss v ss v hv 0110 0010 clear write protection (cwp) v ss v dd v hv 0110 permanently set write protection (pswp) (2) a2 a1 a0 a2 a1 a0 0 read swp v ss v ss v hv 0011 read cwp v ss v dd v hv 0111 read pswp (2) a2 a1 a0 a2 a1 a0 1
spd eeprom operation stts2002 32/52 doc id 15389 rev 5 5.4 software write protect software write-protection allows the bottom half of the memory area (addresses 00h to 7fh) to be temporarily or permanently write protected. software write-protection is handled by three instructions: swp: set write protection cwp: clear write protection pswp: permanently set write protection the level of write-protection (set or cleared) that has been defined using these instructions, remains defined even after a power cycle. figure 10. result of setting the write protection table 24. operating modes mode rw bit bytes initial sequence current address read 1 1 star t, device select, rw = 1 random address read 0 1 start, device select, rw = 0, address 1 restart, device select, rw = 1 sequential read 1 1 similar to current or random address read byte write 0 1 start, device select, rw = 0 page write 0 16 start, device select, rw = 0 ts write 0 2 start, device select, r/w = 0, pointer data, stop ts read 1 2 start, device select, r/w = 1, pointer data, stop default eeprom memory area state before write access to the protect register ai01936c standard array ffh standard array 80h 7fh 00h standard array ffh write protected array 80h 7fh 00h state of the eeprom memory area after write access to the protect register memory area
stts2002 spd eeprom operation doc id 15389 rev 5 33/52 5.4.1 swp and cwp if the software write-protection has been set with the swp instruction, it can be cleared again with a cwp instruction. the two instructions (swp and cwp) have the same format as a byte write instruction, but with a different device type identifier (as shown in ta bl e 2 3 ). like the byte write instruction, it is followed by an address byte and a data byte, but in this case the contents are all ?don?t care? ( figure 11 ). another difference is that the voltage, v hv , must be applied on the a0 pin, and specific logical levels must be applied on the other two (a1 and a2, as shown in ta bl e 2 3 ). 5.4.2 pswp if the software write-protection has been set with the pswp instruction, the first 128 bytes of the memory are permanently write-protected. this write-protection cannot be cleared by any instruction, or by power-cycling the device. also, once the pswp instruction has been successfully executed, the stts2002 spd no longer acknowledges any instruction (with a device type identifier of 0110) to access the write-protection settings. figure 11. setting the write protection reading write-protection status the status of software write protection can be determined using these instructions: read swp: read write protection status read pswp: read permanently set write protection status read swp the controller issues a read swp command. if software write protection has not been set, the device replies to the data byte with an ack. if software write protection has been set, the device replies to the data byte with a noack. read pswp the controller issues a read pswp command. if permanent software write protection has not been set, the device replies to the data byte with an ack. if permanent software write protection has been set, the device replies to the data byte with a noack. start sda line ai01935b ack word address value (don't care) ack data value (don't care) stop ack control byte bus activity master bus activity
spd eeprom operation stts2002 34/52 doc id 15389 rev 5 5.5 write operations following a start condition the bus master sends a device select code with the rw bit reset to 0. the device acknowledges this, as shown in figure 12 , and waits for an address byte. the device responds to the address byte with an acknowledge bit, and then waits for the data byte. when the bus master generates a stop condition immediately after the ack bit (in the ?10 th bit? time slot), either at the end of a byte write or a page write, the internal memory write cycle is triggered. a stop condition at any other time slot does not trigger the internal write cycle. during the internal write cycle, serial data (sda) and serial clock (scl) are ignored, and the device does not respond to any requests. 5.5.1 byte write after the device select code and the address byte, the bus master sends one data byte. if the addressed location is hardware write-protected, the device replies to the data byte with noack, and the location is not modified. if, instead, the addressed location is not write- protected, the device replies with ack. the bus master terminates the transfer by generating a stop condition, as shown in figure 12 . 5.5.2 page write the page write mode allows up to 16 bytes to be written in a single write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits are the same. if more bytes are sent than will fit up to the end of the page, a condition known as ?roll-over? occurs. this should be avoided, as data starts to become overwritten in an implementation dependent way. the bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the device. after each byte is transferred, the internal byte address counter (the 4 least significant address bits only) is incremented. the transfer is terminated by the bus master generating a stop condition. figure 12. write mode sequences in a non write-protected area of spd stop start byte write dev sel byte addr data i n start page write dev sel byte addr data in 1 data in 2 ai01941 stop data in n ack ack ack r/w ack ack ack r/w ack ack
stts2002 spd eeprom operation doc id 15389 rev 5 35/52 5.5.3 write cycle polling using ack during the internal write cycle, the device disconnects itself from the bus and writes a copy of the data from its internal latches to the memory cells. the maximum write time (t w ) is shown in table 2 on page 15 , but the typical time is shorter. to make use of this, a polling sequence can be used by the bus master. the sequence, as shown in figure 13 , is: initial condition: a writ e cycle is in progress. step 1: the bus master issues a start condition followed by a device select code (the first byte of the new instruction). step 2: if the device is busy with the internal write cycle, no ack will be returned and the bus master goes back to step 1. if the device has terminated the internal write cycle, it responds with an ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during step 1). figure 13. write cycle polling flowchart using ack write cycle in progress ai01847c next operation is addressing the memory start condition device select with rw = 0 ack returned yes no yes no restart stop data for the write operation device select with rw = 1 send address and receive ack first byte of instruction with rw = 0 already decoded by the device yes no start condition continue the write operation continue the random read operation
spd eeprom operation stts2002 36/52 doc id 15389 rev 5 5.6 read operations - spd read operations are performed independently of whether hardware or software protection has been set. the device has an internal address counter which is incremented each time a byte is read. figure 14. read mode sequences - spd 1. the seven most significant bits of the dev ice select code of a random read (in the 1 st and 3 rd bytes) must be identical. 5.6.1 random ad dress read - spd a dummy write is first performed to load the address into this address counter (as shown in figure 14 ) but without sending a stop condition. then, the bus master sends another start condition, and repeats the device select code, with the rw bit set to 1. the device acknowledges this, and outputs the contents of the addressed byte. the bus master must not acknowledge the byte, and terminates the transfer with a stop condition. start dev sel (1) byte addr start dev sel data out 1 ai01942 data out n stop start current address read dev sel data out random address read stop start dev sel (1) data out sequential current read stop data out n start dev sel (1) byte addr sequential random read start dev sel (1) data out 1 stop ack r/w no ack ack r/w ack ack r/w ack ack ack no ack r/w no ack ack ack r/w ack ack r/w ack no ack
stts2002 spd eeprom operation doc id 15389 rev 5 37/52 5.6.2 current address read - spd for the current address read operation, following a start condition, the bus master only sends a device sele ct code with the rw bit set to 1. the device acknowledges this, and outputs the byte addressed by the internal address counter. the counter is then incremented. the bus master terminates the transfer with a stop condition, as shown in figure 14 , without acknowledging the byte. 5.6.3 sequential read - spd this operation can be used after a current address read or a random address read. the bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. to terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a stop condition, as shown in figure 14 . the output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. after the last memory address, the address counter ?rolls-over?, and the device continues to output data from memory address 00h. 5.6.4 acknowledg e in read mode for all read commands, the device waits, after each byte read, for an acknowledgment during the 9 th bit time. if the bus master does not drive serial data (sda) low during this time, the device terminates the data transfer and switches to its standby mode. ta bl e 2 5 and table 26 on page 38 show how the ack bits can be used to identify the write- protection status. table 25. acknowledge when writing da ta or defining the write-protection (instructions with r/w bit = 0) status instruction ack address ack data byte ack write cycle(t w ) permanently protected pswp, swp or cwp noack not significant noack not significant noack no page or byte write in lower 128 bytes ack address ack data noack no protected with swp swp noack not significant noack not significant noack no cwp ack not significant ack not significant ack ye s pswp ack not significant ack not significant ack ye s page or byte write in lower 128 bytes ack address ack data noack no not protected pswp, swp or cwp ack not significant ack not significant ack ye s page or byte write ack address ack data ack ye s
spd eeprom operation stts2002 38/52 doc id 15389 rev 5 5.7 initial delivery state - spd the device is delivered with all bits in the memory array set to ?1? (each byte contains ffh). table 26. acknowledge when reading the write protection (instructions with r/w bit=1) status instruction ack address ack data byte ack permanently protected pswp, swp or cwp noack not significant noack not significant noack protected with swp swp noack not significant noack not significant noack cwp ack not significant noack not significant noack pswp ack not significant noack not significant noack not protected pswp, swp or cwp ack not significant noack not significant noack
stts2002 use in a memory module doc id 15389 rev 5 39/52 6 use in a memory module in the dual in line memory module (dimm) app lication, the spd is so ldered directly on to the printed circuit module. the three chip enable inputs (a0, a1, a2) must be connected to v ss or v dd directly (that is without using a pull-up or pull-down resistor) through the dimm socket (see ta bl e 2 7 ). 6.1 programming the spd the situations in which t he spd eeprom is programmed ca n be consider ed under two headings: when the dimm is isolated (not inserted on the pcb motherboard) when the dimm is inserted on the pcb motherboard 6.1.1 dimm isolated with specific programming eq uipment, it is possible to define the spd eeprom content, using byte and page write instructions, and its write-protection using the swp and cwp instructions. to issue the swp and cwp instru ctions, the dimm must be inserted in the application-specific slot where the a0 signal can be driven to v hv during the whole instruction. this programming step is mainly intended for use by dimm makers, whose end application manufacturers will want to clear th is write-protection with the cwp on their own specific programming equipment, to modify the lower 128 bytes, and finally to set permanently the write-protection with the pswp instruction. 6.1.2 dimm inserted in th e application motherboard as the final application cannot drive the a0 pin to v hv , the only possible action is to freeze the write-protection with the pswp instruction. table 27. dram dimm connections dimm position a2 a1 a0 0 v ss (0) v ss (0) v ss (0) 1 v ss (0) v ss (0) v dd (1) 2 v ss (0) v dd (1) v ss (0) 3 v ss (0) v dd (1) v dd (1) 4 v dd (1) v ss (0) v ss (0) 5 v dd (1) v ss (0) v dd (1) 6 v dd (1) v dd (1) v ss (0) 7 v dd (1) v dd (1) v dd (1)
maximum ratings stts2002 40/52 doc id 15389 rev 5 7 maximum ratings stressing the device above the ratings listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. table 28. absolute maximum ratings symbol parameter value unit t stg storage temperature ?65 to 150 c t sld (1) 1. reflow at peak temperature of 260 c. the time above 255 c must not exceed 30 seconds. lead solder temperature for 10 seconds 260 c v io input or output voltage a0 v ss ? 0.3 to 10.0 v others v ss ? 0.3 to 6.5 v v dd supply voltage v ss ? 0.3 to 6.5 v i o output current 10 ma p d power dissipation 320 mw ja thermal resistance 87.4 c/w
stts2002 dc and ac parameters doc id 15389 rev 5 41/52 8 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in ta bl e 2 9 . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. figure 15. ac measurement i/o waveform table 29. operating and ac measurement conditions parameter conditions unit v dd supply voltage 2.3 to 3.6 v operating temperature ?40 to 125 c input rise and fall times 50 ns load capacitance 100 pf input pulse voltages 0.2v dd to 0.8v dd v input and output timing reference voltages 0.3v dd to 0.7v dd v input levels input and output timing reference levels 0.8 * v dd 0.2 * v dd 0.7 * v dd 0.3 * v dd ai14011 table 30. dc/ac characteri stics - temperature sens or component with eeprom sym description test condition (1) min typ (2) max unit v dd supply voltage 2.3 3.3 3.6 v i dd v dd supply current (no load) eeprom active (3) f = 400 khz 0.4 2.0 ma eeprom standby, f = 400 khz 160 300 a i dd1 shutdown mode supply current eeprom standby, ts shutdown 3.0 5 a i ili input leakage current (scl, sda) v in = v ss or v dd 5 a i ilo output leakage current v out = v ss or v dd , sda in hi-z 5 a v por power on reset (por) threshold v dd falling edge: dn package 1.75 v
dc and ac parameters stts2002 42/52 doc id 15389 rev 5 b-grade accuracy for corresponding range 2.3 v v dd 3.6 v +75 c < t a < +95 0.5 1.0 c +40 c < t a <+ 125 1.0 2.0 c ?40 c < t a < +125 2.0 3.0 c resolution 0.5 0.25 0.0625 c/lsb 91012bits t conv conversion time 10-bit - default 125 ms smbus/i 2 c interface v ih input logic high scl, sda, a0-a2 0.7v dd v dd + 1 v v il input logic low scl, sda, a0-a2 ?0.5 0.3v dd v c in (4) smbus/i 2 c input capacitance 5 pf f scl smbus/i 2 c clock frequency 10 400 khz t timeout smbus timeout temperature sensor only 25 35 ms v hv a0 high voltage v hv v dd + 4.8 v 7 10 v v ol1 low level voltage, event i ol = 2.1 ma 0.4 v v ol2 low level voltage, sda i ol = 2.1 ma 0.4 v i ol = 6 ma 0.6 v z ail (4) (a0, a1, a2) input impedance v in < 0.3 v dd 30 k z aih (4) (a0, a1, a2) input impedance v in > 0.7 v dd 800 k t sp (4) spike suppression pulse width of spikes that must be suppressed by the input filter input filter on scl and sda 50 ns v hyst (5) input hysteresis (scl, sda) ts only 0.05v dd v 1. guaranteed operating temperature for combined module: t a = ?40 c to 125 c; v dd = 2.3 v to 3.6 v (except where noted). 2. typical numbers taken at v dd = 3.3 v, t a = 25 c. 3. read current only 4. verified by design and c haracterization, not necessa rily tested on all devices 5. v hyst parameter is optional in th e jedec tse2002a2 specifications table 30. dc/ac characteristic s - temperature sensor com ponent with eeprom (continued) sym description test condition (1) min typ (2) max unit
stts2002 package mechanical data doc id 15389 rev 5 43/52 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
package mechanical data stts2002 44/52 doc id 15389 rev 5 figure 16. tdfn8 ? 8-lead thin dual flat, no-lead (2 mm x 3 mm) package outline (dn) note: jedec mo-229, variation wced-3 proposal note: jedec mo-229, variation wced-3 proposal 8089094_a table 31. tdfn8 ? 8-lead thin dual flat, no-lead (2 mm x 3 mm) mechanical data (dn) sym mm inches min typ max min typ max a 0.70 0.75 0.80 0.028 0.030 0.031 a1 0.00 0.00 0.05 0.000 0.000 0.002 a3 0.20 0.008 b 0.20 0.25 0.30 0.008 0.010 0.012 d 1.95 2.00 2.05 0.077 0.079 0.081 d2 1.35 1.40 1.45 0.053 0.055 0.057 e 2.95 3.00 3.05 0.116 0.118 0.120 e2 1.25 1.30 1.35 0.049 0.051 0.053 e0.50 0.020 l 0.30 0.35 0.40 0.012 0.014 0.016 ddd 0.08 0.003
stts2002 package mechanical data doc id 15389 rev 5 45/52 figure 17. dn package topside marking information (tdfn8) 1. temperature grade and package b = b-grade, stacked 2 = minimum operating voltage of 2.3 v dn = 0.80 mm tdfn package 2. device name tse2 = stts2002 3. traceability codes ai13907b tse2 (2) xxxx (3) b2dn (1)
package mechanical data stts2002 46/52 doc id 15389 rev 5 the landing pattern recommendations per the jedec proposal for the tdfn package (dn) are shown in figure 18 . the preferred implementation with wide corner pads enhances device centering during assembly, but a narrower option is defined for modules with tight routing requirements. figure 18. landing pattern - tdfn8 package (dn) e/2 e/2 e2 k k e2/2 e2/2 e2 d2/2 d2 d2/2 l l e b b b2 b4 k2 k2 k2 e3 e3 e4 ai14000
stts2002 package mechanical data doc id 15389 rev 5 47/52 ta bl e 3 2 lists variations of landing pattern implementations, ranked as ?preferred? and minimum acceptable? based on the jedec proposal. table 32. parameters for landing pattern - tdfn8 package (dn) parameter description dimension min nom max d2 heat paddle width 1.40 - 1.60 e2 heat paddle height 1.40 - 1.60 e3 heat paddle centerline to contact inner locus 1.00 - - l contact length 0.70 - 0.80 k heat paddle to contact keepout 0.20 - - k2 contact to contact keepout 0.20 - - e contact centerline to contact centerline pitch for inner contacts - 0.50 - b contact width for inner contacts 0.25 - 0.30 e2 landing pattern centerline to outer contact centerline, ?minimum acceptable? option (1) -0.50- b2 corner contact width, ?minimum acceptable option? (1) 0.25 - 0.30 e4 landing pattern centerline to outer contact centerline, ?preferred? option (2) -0.60- b4 corner contact width, ?preferred? option (2) 0.45 - 0.50 1. minimum acceptable option to be used when routing prevents preferred width contact. 2. preferred option to be used when possible.
package mechanical data stts2002 48/52 doc id 15389 rev 5 figure 19. carrier tape for tdfn8 package t k 0 p 1 a 0 b 0 p 2 p 0 center line s of cavity w e f d top cover tape u s er direction of feed am0 3 07 3 v1 table 33. carrier tape dimensions tdfn8 package package w d e p 0 p 2 fa 0 b 0 k 0 p 1 tunit bulk qty tdfn8 8.00 + 0.30 ?0.10 1.50 +0.10/ ?0.00 1.75 0.10 4.00 0.10 2.00 0.10 3.50 0.05 2.30 0.10 3.20 0.10 1.10 0.10 4.00 0.10 0.30 0.05 mm 3000
stts2002 package mechanical data doc id 15389 rev 5 49/52 figure 20. reel schematic note: the dimensions given in ta b l e 3 4 incorporate tolerances that cover all variations on critical parameters. a d b f u ll r a di us t a pe s lot in core for t a pe s t a rt 2.5mm min.width g me asu red at h ub c n 40mm min. acce ss hole at s lot loc a tion t am0492 8 v1 table 34. reel dimensions for 8 mm carrier tape - tdfn8 package a (max) b (min) c d (min) n (min) g t (max) 180 mm (7-inch) 1.5 mm 13 mm 0.2 mm 20.2 mm 60 mm 8.4 mm + 2/?0 mm 14.4 mm
part numbering stts2002 50/52 doc id 15389 rev 5 10 part numbering table 35. ordering information scheme for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. example: stts2002 b 2 dn 3 f device stts2002 accuracy grade b: maximum accuracy 75 c to 95 c = 1 c voltag e 2 = 2.3 v - 3.6 v package dn = tdfn8 temperature range 3 = ?40 c to 125 c shipping method f = ecopack ? package, tape & reel packing
stts2002 revision history doc id 15389 rev 5 51/52 11 revision history table 36. document revision history date revision changes 11-feb-2009 1 initial release. 08-oct-2009 2 updated features , section 1 , section 2.1 , section 2.2.5 , section 3.3 , section 4.1 , section 4.8 , section 5.4 , section 5.4.2 , section 5.5.2 , section 5.5.3 , section 6 , figure 3 , 7 , 19 , ta bl e 2 , 3 , 5 , 6 , 7 , 9 , 12 , 13 , 24 , 25 , 28 , 29 , and 30 ; moved figure 14 , section 5.7 , ta bl e 2 5 and 26 ; added ta b l e 3 3 ; removed section on ?alert reponse address (ara)?; reformatted document. 19-oct-2009 3 updated figure 17 . 13-sep-2010 4 document updated to full datasheet; updated figure 3 , ta bl e 3 5 ; section 4.8: smbus timeout ; minor textual changes; added figure 20 , ta bl e 3 4 , note to ta bl e 3 . 21-mar-2011 5 updated figure 17: dn package topside marking information (tdfn8) and document status.
stts2002 52/52 doc id 15389 rev 5 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2011 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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